Information for "An efficient 10GBASE-T ethernet LDPC decoder design with low error floors"
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Basic information
Display title | An efficient 10GBASE-T ethernet LDPC decoder design with low error floors |
Default sort key | An efficient 10GBASE-T ethernet LDPC decoder design with low error floors |
Page length (in bytes) | 144 |
Page ID | 1721 |
Page content language | en - English |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 0 |
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Edit history
Page creator | Wikiworks (talk | contribs) |
Date of page creation | 04:29, April 16, 2018 |
Latest editor | Wikiworks (talk | contribs) |
Date of latest edit | 04:29, April 16, 2018 |
Total number of edits | 1 |
Total number of distinct authors | 1 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
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